1. Field of the invention
The present invention relates to a bypass circuit on a metal-oxide semiconductor (MOS) transistor, more specifically, to a bypass circuit for reducing plasma damage to a gate oxide of the MOS transistor.
2. Description of the Prior Art
A metal-oxide semiconductor (MOS) is a common electrical device used in integrated circuits. The MOS transistor is a unit, having four nodes, formed by a gate, a source and a drain. By utilizing channel effects generated by the gate of the MOS under different gate voltages, the MOS is often made to function as a digitalized solid switch applied on various integrated circuits of memory or logic devices.
Please refer to FIG. 1 to FIG. 4 of the cross-sectional views of manufacturing a MOS transistor according to the prior art. As shown in FIG. 1, a silicon substrate 12, a gate oxide layer 14 and a gate 16 are formed, respectively, on a semiconductor wafer 10.
As shown in FIG. 2, a first ion implantation process 18 is performed to form two doped areas, used as a lightly doped drain (LDD) 22 of the MOS transistor, located on either side of the gate 16 on the surface of the silicon substrate 12. The LDD 22 is also called a source-drain extension (SDE).
As shown in FIG. 3, a spacer 24, composed of an insulating material, is then formed on either vertical wall of the gate 16. As shown in FIG.4, a second ion implantation process 26 is used to form two doped areas, used as a source 27 and a drain 28 of the MOS transistor, positioned on portions of the silicon substrate 12 adjacent to the spacer 24 to complete the manufacturing of the MOS transistor.
Please refer to FIG. 5 of the cross-sectional view of performing a self-alignment silicide process on a MOS transistor.
The self-alignment silicide (salicide) process is often performed after the formation of the MOS transistor to reduce the contact resistance of each silicon surface on the MOS transistor. Therefore, a silicide layer 32 is formed on the surface of the gate 16, the source 27 and the drain 28 of the MOS transistor after the self-alignment silicide process.
However, a huge amount of ions accumulate in the gate 16 as a result of ultraviolet (UV) radiation during a plasma etching, ion bombardment and photo process. The accumulated ions may penetrate from the gate 16 into the gate oxide layer 14 and the silicon substrate 12 so as to cause the antenna effect and leading to the degradation of the gate oxide layer 14, or the so-called plasma process induced damage (PPID), to produce defective functioning of the MOS transistor.